🔹 Position: Verification Engineer (Questa Verification IP Team) 🏢 Company: Siemens EDA 📍 Location: Noida 🕐 Experience: 0-5 Years 💼 Job Role: ✅ Design & develop verification components ✅ Work with SystemVerilog (SV), UVM, Assertions, Coverage, Test Plans, BFM Design, Debugging, Logging ✅ Collaborate with TMEs, Field AEs & Customers to resolve issues 🎓 Eligibility: 📚 Education: B.Tech/M.Tech (Electronics, CS, Electrical, or equivalent) 🛠 Skills: SystemVerilog, UVM, PCIe, USB, SATA, NVMe, Flash, DIMM 📩 Apply Now! 📧 Send your resume to [email protected] 🔖 #hiring #siemenseda #uvm #verilog #noida #verification