Cadence (Invecas) in Hyderabad is looking to hire Physical Design Engineers with 5-8 years of experience. Responsibilities: - Delivering Block level Netlist to GDS - Handling Subsystem level floorplan, PnR, and timing closure - Conducting FCFP/FCI/FCT activities - Leading/Guiding a team of 2-3 Engineers Required Skills: - 5+ years of experience in PnR and STA - Hands-on experience in RTL/Netlist to GDS delivery of blocks - Good understanding of DFT stitching and clock tree strategies - Strong at resolving density and congestion issues - Experience with complex blocks floorplan, PnR, and STA - Capable of handling PV and IREM fixes along with timing - Exposure to technologies like 7/6nm, 5/4nm & 3/2nm - Knowledge of TCL and PERL scripting for writing scripts - Familiarity with Cadence EDA tool set for PD Optional Skills: - Hands-on experience in low power designs - Experience in subsystem level activities - Familiarity with Flat Chip or small hier chip FC activities - Expertise in complex IP integration such as DDR and PCIe - Experience in guiding freshers/interns If you are interested, please share your updated profile with [email protected].