www.vlsijobseekers.com
February 26, 2025 at 09:01 AM
👉 Question:
What will be the output of the following SystemVerilog code?
module test;
int a = 5;
initial begin
fork
a = a + 1;
a = a * 2;
join_none
#1;
$display("a = %0d", a);
end
endmodule
A) 6
B) 12
C) 10
D) Undefined behavior
4️⃣
🅱️
4⃣
2⃣
🅰️
2️⃣
❤️
📞
34