🔎 SystemVerilog Quiz Challenge! 🏆 Think you’re a SystemVerilog pro? Let’s put your knowledge to the test with these two tricky questions! 1️⃣ Question 1 Why was the logic data type introduced in SystemVerilog? A) To represent analog signals B) To replace reg and wire types for simpler syntax C) To provide a 4-state data type that eliminates confusion between reg and wire D) To enable multi-dimensional array declarations 2️⃣ Question 2 🚀 Which statement about mailboxes in SystemVerilog is INCORRECT? A) A mailbox enables inter-thread communication by storing and retrieving messages. B) The get() method blocks execution until an item is available. C) The try_peek() method removes the item from the mailbox if it exists. D) A mailbox can be bounded (fixed size) or unbounded. 💡 Think carefully before answering—many get this wrong! 😏 💬 Drop your answers in the comments! Let’s see who can get both right. ✔️ Correct answers will be revealed tomorrow! 🚀