The Department of Electronics and Communication Engineering, National Institute of Technology Calicut is delighted to announce a "5-Day Short-Term Training Programme (STTP)" on: "Custom IC Design and Layout using Standard 180nm PDK" 17 June 30-July 4, 2025 National Institute of Technology Calicut In light of India's booming Semiconductor Mission and the Chips to Startup (C2S) programme, this workshop is designed to provide hands-on training in: * Schematic capture * Pre-layout and post-layout simulations * Custom layout design * Physical verification * GDSII generation - ready for fabrication! Who Should Attend? * UG/PG/PhD students * Faculty members in VLSI, ECE, EE, CS * Industry professionals and R\&D engineers Register here: https://docs.google.com/forms/d/e/1FAIpQLScSIGA1XuzodnMg_mPOShcS39M4_7XdwEGBIfK9C0vMcQbfEg/viewform Last date: June 20, 2025 Certificates will be issued to all registered participants upon completion of course Sessions by: Dr. Gajendranath Chaudhury (IIT Hyderabad) Prof. Srihari Rao Patri (NIT Warangal) Dr. Kapil Jainwal (IIT Hyderabad) Dr. Suresh P R (Exiger Technologies Pvt Ltd) & Faculties from NIT Calicut Coordinators: Dr. Bhuvan B & Dr. Dhanaraj K J E Email: [email protected] +91 9495575325 _*📢 Stay updated on Physics opportunities via Whatsapp:*_ https://whatsapp.com/channel/0029VahVVrV7j6g3vmLege1c