
The Silicon Sandbox
June 6, 2025 at 08:56 AM
https://careers.google.com/jobs/results/104984840440292038-asic-rtl-design-engineer/?src=Online/LinkedIn/linkedin_us&utm_source=linkedin&utm_medium=jobposting&utm_campaign=contract
*Minimum qualifications:*
* Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience.
* 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
* Experience in ARM-based SoCs, interconnects and ASIC methodology.

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